Design test pattern embedding hardware to control an LFSR with the characteristic polynomial f(x) = 1 + x + x 3 to produce an all-zero test pattern.

Design test pattern embedding hardware to control an LFSR with the characteristic polynomial f(x) = 1 + x + x3 to produce an all-zero test pattern. This problem also requires you to design the actual LFSR. Show the diagram of the hardware and also the generated patterns. Is this less hardware than just implementing a 3-bit binary counter?
 
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